The present invention generally relates to semiconductor devices and more particularly, to a semiconductor memory device having an addressable memory.
In order to prevent writing of unwanted data into a memory array, it is often necessary to prevent or invalidate a memory write operation. Without a timely memory write invalidation, data integrity becomes an issue, because unwanted data may be written into the memory array at the risk of corrupting valid stored data. Situations in which a timely write invalidation is useful include circumstances when valid data and/or a valid data address are not available, or where a microprocessor is in a test mode.
The conventional implementation of a memory array write invalidation is accomplished at the expense of an increase in component density, an increase in memory array power consumption, and added delay in certain memory operations. The classic implementation of a write invalidation is to provide circuitry to directly cancel each write word line asserted. This can be accomplished with a control signal that is tied to each row decoder of the memory array. Another classic write invalidation technique is to allow the write word lines to assert, but to directly invalidate the data being written. Because memory density, device power dissipation, and device operating speeds are at a premium in today""s marketplace, the inefficiencies of the conventional write invalidation techniques are an undue burden on a memory array architecture.
The present invention addresses the above-described limitations of conventional systems that facilitate memory array write invalidation operations. The present invention provides an approach to enable a memory write invalidation operation to occur outside of the memory array before a memory write word line is asserted.
In one embodiment of the present invention, an apparatus provides a decoding circuit that performs row predecoding and word line assertion. The predecode circuit invalidates a memory row predecode operation before the predecode operation occurs. In the predecode circuit, one or more switches are adapted to receive a write control signal. When the switches receive a control signal to invalidate a write operation, the write row predecoder is prevented from asserting. Further, the apparatus provides a row decode circuit to generate a write word line when a valid control signal is asserted at the switches.
The above described approach benefits a semiconductor device having an addressable memory array because the memory write invalidation occurs before any write row predecode lines are asserted. As a result, a memory device may have a reduced die area because an additional input at each row decoder in the memory array is no longer needed to invalidate a memory write operation.
In accordance with another aspect of the present invention, a method is performed in a storage device having addressable rows such that a memory write operation is invalidated before a write row predecode operation occurs. The storage device receives a memory row address at one or more dynamic input nodes to initiate the generation of a write word line. So long as a valid write control signal is asserted at the dynamic input nodes, a valid write word line is asserted to the storage device. A dynamic latch is coupled to the dynamic input node. Should the valid write control signal be deasserted at the dynamic input nodes, the dynamic latch latches are reset, which, in turn, prevents any of the row predecode inputs from asserting, and, in turn, prevents any write word line from asserting.
The above-described approach benefits a microprocessor architecture that processes speculative data in that unwanted data is prevented from being written into the memory array before a memory write predecode occurs; thus, there is a minimal impact on the processing time of the microprocessor. As a result, microprocessor processing efficiency is increased and power consumption is decreased.
Moreover, the placement of a level sensitive latching device before any of the row decoding circuitry allows the memory row address to be held constant at the inputs of the row decoding circuitry for an entire clock phase. In this manner, the memory row decode operation may occur for an entire clock phase without having the memory row address, at the input to the memory row decoder, change before the decode operation is complete.